What is the BIT file format?
A .bit file is a binary FPGA configuration bitstream produced by Xilinx (now AMD) EDA tools. It encodes the complete programming data for an FPGA device - routing, logic cell configuration, I/O settings, and RAM initialization - and is loaded into the chip to define its hardware behavior.
The file has a two-part structure: a variable-length ASCII TLV (Tag-Length-Value) header recording the design name, target device, and build date/time, followed by the binary bitstream payload. The payload begins with 0xFF dummy padding bytes, then the sync word 0xAA995566, then type-1 and type-2 configuration packets that write to internal FPGA registers (FAR, FDRI, CMD, IDCODE).
AMD Vivado Design Suite generates .bit files for 7-series, UltraScale, and UltraScale+ FPGAs. Legacy ISE Design Suite (v14.7, still downloadable but no new releases since 2013) produces .bit files for older families such as Spartan-6 and Virtex-4/5/6. For Versal devices the successor is .pdi. Related formats include .bin (raw bitstream without the TLV header, used for SPI flash programming).
Optional AES-256 encryption and HMAC authentication protect against IP theft. A CRC is appended to the bitstream; the FPGA verifies it during configuration load. Open-source tools such as openFPGALoader and xc3sprog can program FPGAs directly from .bit files.
Security & safety
RISK: LOWBinary file that can only configure FPGA hardware - cannot execute on a PC CPU. No malware risk from opening the file in a viewer. Loading a malicious bitstream onto FPGA hardware could subvert the hardware's function, but this is a physical-access attack scenario.
Format details
in a nutshell- X11 Bitmap (XBM) - Some sources associate .bit with X11 bitmap image format (plain-text ASCII pixel art); this is rare and the format normally uses .xbm.
- BitTorrent Incomplete Download - Some BitTorrent clients use .bit as a partial download marker - unrelated to FPGA.
Programs that open BIT files
Windows2 apps
AMD Vivado Design Suite
Freemium Open Hardware Manager, connect JTAG, right-click device > Program Device > select .bit file.
Xilinx ISE Design Suite 14.7
Freemium Use iMPACT programmer: right-click FPGA in boundary-scan chain > Assign New Configuration File > select .bit. 
Linux3 apps
openFPGALoader
Open-source openFPGALoader -b <board> design.bit - supports Xilinx BIT files via JTAG/USB. Technical details
deep spec| Encoding | Binary |
| Byte order | Big-endian (32-bit configuration packets) |
| Header format | ASCII TLV - fields: 'a' design name, 'b' target device, 'c' build date, 'd' build time, 'e' payload byte length |
| Sync word | 0xAA995566 - marks start of binary bitstream payload |
| Bitstream preamble | 0xFF dummy bytes preceding the sync word |
| Encryption support | Optional AES-256; encryption key stored in BBRAM or eFUSE on the device |
| Authentication | Optional HMAC for encrypted bitstreams |
| Integrity check | CRC appended at end of bitstream; FPGA verifies on configuration load |
| Compression option | Vivado supports optional compressed bitstreams for select device families |
| FPGA families | Spartan-6 (ISE); 7-series, UltraScale, UltraScale+ (Vivado) |
| Typical file size | 300 KB - 100 MB (Spartan: ~300 KB; large UltraScale+: 50-100 MB) |
| Generating tools | AMD Vivado (current); Xilinx ISE 14.7 (legacy, no releases since October 2013) |
| Raw format alternative | .bin - no TLV header; used for direct SPI flash programming |
| Versal successor format | .pdi (Program Device Image), introduced with Versal ACAP family in 2020 |
| Released | ~1985 (with early Xilinx FPGA toolchain) |
| Latest version | Vivado 2025.1 bitstream (7-series, UltraScale, UltraScale+, Versal) |
| Specification | docs.amd.com |
BIT conversions
Community Q&A
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